This application is related to thin film transistors, particularly for active matrix liquid crystal displays.
In conventional process for making amorphous silicon (a-Si) thin film transistors (TFT), the TFT has a very large overlap region between the gate and source, and between the gate and the drain. This overlap results in a very large stray capacitance, which degrades the high frequency response and introduces unacceptable DC voltage levels when the transistors are used in a liquid crystal display device. This stray capacitanace should therefore be minimized. The adverse effect due to the gate overlap can be reduced by using self-aligned gate.
In a U.S. patent application Ser. No. 07/495,829, now abandoned, "Process for Making a Self-Aligned Inverted Coplanar/Staggered Amorphous Silicon Thin Film Transistors" it has been disclosed a method for making a self-aligned TFT for reducing the overlap capacitance. The TFT structure is shown in FIG. 1. Due to the novel self-aligned process, the capacitance between the a-Si:H channel 8 and the source/drain n+a-Si:H electrodes 12 is minimized. However, there is an extension Lp of the n+a-Si:H source/drain electrodes Lp over the two ends of the a-Si:H channel 8. This extension exists because the window opening 10 in the n+a-Si:H and the conducting layer 14 over the top of the a-Si:H channel is patterned with a mask over the structure which is not self-aligned with the gate electrode 4. To avoid misalignment, window opening 10 must be made shorter than the channel length itself, The extension results in an overlap Lp which gives rise to substantial capacitance which is undesirable as explained earlier.